FIG. 1 shows a conventional memory chip U, which is embodied for example as a DRAM (dynamic random access memory) memory chip. The memory chip U comprises a memory cell array SZF, in which memory cells SZ are arranged in matrix-like fashion along word lines WL and bit lines BL. A memory cell SZ comprises a selection transistor AT and a storage capacitor SC. In the case of a read or write access, the selection transistor AT is controlled to be put into an on state by a corresponding control signal on the word line WL. Consequently, the storage capacitor SC is connected to the bit line BL via the selection transistor AT controlled in the on state. In the event of a read access, data amplified by a sense amplifier (not illustrated in FIG. 1) can be fed via the bit line BL to a data terminal DIO for outputting. In the event of a write access, via the selection transistor AT controlled in the on state, data can be written to one of the memory cells SZ from the data terminal DIO via the bit line BL.
The memory chip U furthermore comprises a control circuit S with control terminals S1, S2, S3 and S4, to which external control signals CS, WE, RAS and CAS can be applied. Address terminals A0, . . . , An for application of address signals AS0, . . . , ASn are connected to an address register AR. An address signal presented at the address terminals is forwarded as a row address to a row decoder RD and as a column address to a column decoder CD.
Write and read accesses to the memory chip are synchronized to a clock signal CLK at a clock terminal T. In the event of a write access to a memory cell of the memory chip U, address signals AS0, . . . , ASn are supplied the address terminals A0, . . . , An to select one of the memory cells of the memory cell array SZF for the write access.
For selection of the memory chip U for the write access, a chip select signal CS is applied to the control terminal S1. Simultaneously with this, the row select signal RAS is applied to the control terminal S3. According to the applied row address, a word line WL of the memory cell array SZF is activated by the row decoder RD. As a result, all selection transistors AT which are connected along the activated word line are controlled to be put into an on state. For selection of a specific memory cell along the activated word line, subsequently the chip select signal CS is applied to the control terminal S1, the write enable signal WE is applied to the control terminal S2 and the column select signal CAS is applied to the control terminal S4. According to the column address applied to the address terminals, the column decoder CD activates one of the bit lines BL of the memory cell array for the write access. That memory cell that lies at a crossover point between the activated word line and the activated bit line is thereby selected for a write access.
After a precharge operation, during which all the bit lines of the memory cell array are brought to a common voltage, a read access can be made to one of the memory cells. For selection of the memory cell to be read, the address terminals A0, . . . , An are again driven by an address signal AS0, . . . , ASn containing a row address and a column address. For selection of the memory chip U for the read access, the control circuit S is driven by the chip select signal CS at the control terminal S1 and by the row select signal RAS at the control terminal S3. According to the applied row address, the row decoder RD selects one of the word lines WL and, by means of a corresponding voltage potential on the selected word line, activates all the memory cells SZ which are connected along the selected word line. Thereafter, the chip select signal CS is applied to the control terminal S1 and the column select signal CAS is applied to the control terminal S4. The column decoder CD in response selects one of the bit lines BL according to the column address. The memory cell that lies at a crossover point between the selected word line and the selected bit line is thereby selected for the read access.
Memory chips of this type are generally combined on a semiconductor memory module to form a larger memory unit. The individual memory chips on the semiconductor memory module can no longer be directly driven externally with control and address signals, but rather are shielded from the outside world by means of a control chip. A memory controller accesses the control chip, which in turn drives the individual memory chips on the semiconductor memory module for a read and write access with control signals, address signals and data signals.
FIG. 2 shows a conventional semiconductor memory module HSM, in which a control chip HC is embodied as a hub chip, by way of example, and memory chips U1, . . . , U36 are arranged on a module circuit board MP. The semiconductor memory chips in the example of FIG. 2 have a ×4 organizational form. In the case of this organizational form, four items of data are simultaneously read into the memory cells of a memory chip in the event of a write access, and four items of data are simultaneously read out from the memory cells of a memory chip in the event of a read access. Those memory chips which are simultaneously addressed by the memory controller or the control chip HC in the event of an access to the semiconductor memory module are combined in groups, so-called ranks. The number of memory chips belonging to a rank is dependent on the bus width of the access bus with which the memory controller accesses the semiconductor memory module, and on the organizational form of the memory chips on the memory module. If the control chip is driven by a memory controller via an access bus having a bus width of 72 bits and the memory chips have the ×4 organizational form, it is possible, in the event of a read or write access to the semiconductor memory module, for four items of data in each case to be simultaneously read out from 18 memory chips or for four items of data in each case to be simultaneously written to 18 memory chips. A rank therefore comprises 18 memory chips. The semiconductor memory module of FIG. 2 comprises two ranks each having 18 memory chips and therefore represents a 2R×4 module configuration.
The module circuit board MP of FIG. 2 has a top side TOP and a bottom side BOT. In accordance with an industry standard for a memory module of the 2R×4 module configuration, the control chip HC is arranged in the center on the top side TOP of the module circuit board. The individual memory chips U1, . . . , U4, U9, . . . , U12, U17, . . . , U20 and U25, . . . , U28 are arranged in two rows on the top side of the module circuit board on the left and right of the control chip.
The rest of the memory chips U5, . . . , U8, U13, . . . , U16, U21, . . . , U24 and U29, . . . , U32 are likewise arranged in two rows on the bottom side BOT of the module circuit board. The individual memory chips each contain a memory cell array SZF, as shown in FIG. 1, for storing data. The memory chips U33, U34, U35 and U36, which, in accordance with an industry standard, are positioned on the bottom side BOT of the module circuit board directly under the control chip HC, are embodied as ECC (error correcting code) memory chips. Data for error correction are stored in the memory cells of their memory cell array. When reading from a memory chip, a datum read out erroneously from a memory chip can be corrected by the control chip HC by means of such error correction data stored in the ECC memory chips.
In order to drive the individual memory chips and also the ECC memory chips with control and address signals, the control chip HC is connected to the individual memory chips and the ECC memory chips via a control bus CAB. The design of the control bus CAB for a memory module of the 2R×4 module configuration is explained hereinafter with reference to FIGS. 3 and 4.
FIG. 3 shows a conventional control chip HC. The control chip HC is connected via the control bus CAB to the memory chips U1, . . . , U4 in a row R11 on the top side TOP of the module circuit board, to the memory chips U9, . . . , U12 in a row R12 on the top side TOP of the module circuit board, to the memory chips U5, . . . , U8 in a row R21 on the bottom side BOT of the module circuit board, to the memory chips U13, . . . , U16 in a row R22 on the bottom side of the module circuit board and to the two ECC memory chips U33 and U34.
FIG. 4 shows a detail from a cross section through a conventional module circuit board MP. The control chip HC and also the two memory chips U1 and U2 are arranged on the top side of the module circuit board. The ECC memory chip U33 is arranged on the bottom side of the module circuit board below the control chip HC. The memory chips U5 and U6 are arranged on the bottom side of the module circuit board under the memory chips U1 and U2. The control chip HC is connected to a contact-making hole V0 via a short conductor track LHC on the top side TOP of the module circuit board MP. The control chip HC is connected to the control bus CAB via the short conductor track LHC on the top side of the module circuit board and the contact-making hole V0.
The control bus CAB runs on an internal layer INT1 of the module circuit board. At the contact-making hole V1, the control bus CAB branches into a partial bus CAB1 and a partial bus CAB2. The memory chips U, . . . , U4 of the row R11 on the top side of the module circuit board, the memory chips U5, U8 of the row R21 on the bottom side of the module circuit board and the ECC memory chip U33 are connected to the partial bus CAB1. FIG. 4 illustrates an example of only part of the partial bus CAB1.
The partial bus CAB1 runs on the internal layer INT1 as far as a contact-making hole V1. The memory chip U1 is connected to the partial bus CAB1 via a short conductor track L1 on the top side of the module circuit board and the contact-making hole V1. The memory chip U5 is connected to the partial bus CAB1 via a short conductor track L5 on the bottom side of the module circuit board and the contact-making hole V1. Proceeding from the contact-making hole V1, the partial bus CAB1 runs further along the internal layer INT1 to contact-making holes V11, V12 and V13. The memory chips U2 and U6 are connected to the partial bus CAB1 via the contact-making hole V11 and a short conductor track L2 on the top side of the module circuit board and, respectively, a short conductor track L6 on the bottom side of the module circuit board. The memory chips U3 and U7 are connected to the partial bus CAB1 via the contact-making hole V12 and a short conductor track L3 on the top side of the module circuit board and, respectively, a short conductor track L7 on the bottom side of the module circuit board. The memory chips U4 and U8 are connected to the partial bus CAB1 via the contact-making hole V13 and a short conductor track L4 on the top side of the module circuit board and, respectively, a short conductor track L8 on the bottom side of the module circuit board. Through a contact-making hole V14, the partial bus CAB1 is connected to the top side of the module circuit board and from there, via a short conductor track LR, to a terminating resistor R at its end ECAB1. The terminating resistor R is connected to a voltage supply Vtt.
The partial bus CAB2 runs on a further internal layer INT2 of the module circuit board. Proceeding from the contact-making hole V0, the partial bus CAB2 runs as far as a contact-making hole V2. The memory chips U9 and U13 are connected to the partial bus CAB2 via the contact-making hole V2 and a short conductor track L9 on the top side of the module circuit board and, respectively, a short conductor track L13 on the bottom side of the module circuit board. From the contact-making hole V2, the partial bus CAB2 runs further on the internal layer INT2 of the module circuit board via further contact-making holes V21, V22 and V23 as far as a contact-making hole V24. The memory chips U10 and U14 are connected to the partial bus CAB2 via the contact-making hole V21 and a short conductor track L10 on the top side of the module circuit board and, respectively, a short conductor track L14 on the bottom side of the module circuit board. The memory chips U11 and U15 are connected to the contact-making hole V22 via the contact-making hole V22 and a short conductor track L11 on the top side of the module circuit board and, respectively, a short conductor track L15 on the bottom side of the module circuit board. The memory chips U12 and U16 are connected via a short conductor track L12 on the top side of the module circuit board and, respectively, a short conductor track L16 on the bottom side of the module circuit board and the contact-making hole V23 to the internal layer INT2 and thus to the partial bus CAB2. An end ECAB2 of the partial bus CAB2 is terminated via a terminating resistor R and a voltage supply Vtt via the contact-making hole V24 and a short conductor track LR′ on the top side of the module circuit board.
A branch of the partial bus CAB1, proceeding from the contact-making hole V1, runs along the internal layer INT2 in the backward direction of the ECC memory chip U33 as far as a contact-making hole V20 positioned below the contact-making hole V0 for connecting the ECC memory chip U33 to the control bus CAB. The ECC memory chip U33 is connected via a short conductor track L33 and the contact-making hole V20 to the branch of the partial bus CAB1 which runs on the internal layer INT2. The ECC memory chip U34 is also connected to the control bus CAB in a similar manner. Proceeding from the contact-making hole V2, a branch of the partial bus CAB2 runs along the internal layer INT1 of the module circuit board in the backward direction of the ECC memory chip U34 as far as a contact-making hole V10 and from there via a short conductor track L34 on the bottom side of the module circuit board to the ECC memory chip U34.
As is illustrated in FIGS. 3 and 4, the control bus CAB branches into a partial bus CAB1 and a partial bus CAB2 in the region of the contact-making hole V0. Proceeding from the contact-making hole V1, a branch of the partial bus CAB1 runs on the internal layer INT2 back to the ECC memory chip U33 again, which is positioned under the control chip HC on the module circuit board. Likewise, proceeding from the contact-making hole V2, a branch of the partial bus CAB2 runs via the internal layer INT1 back to the ECC memory chip U34 again, which is likewise arranged under the control chip HC on the bottom side of the module circuit board.
The contact-making holes V0, V1, V2, V10 and V20 are all arranged in a narrow region around the control chip HC. FIG. 5 shows a detail from an internal layer of a conventional module circuit board with contact-making holes and conductor tracks in a region B in the vicinity of the control chip HC. As shown in FIG. 5, a shortage of space occurs in this region by virtue of the numerous terminal connections of the control chip HC and also the numerous contact-making holes and bus lines, in particular due to the bus lines that run back in the direction of the ECC memory chips for the purpose of connecting to the ECC memory chips. Therefore, it is not possible to implement the branches of the partial buses CAB1 and CAB2 (for connecting the ECC memory chips to the control chip) in accordance with the standard shown in FIG. 3. In a 2R×4 module configuration this situation arises particularly when the input and output terminals of the control chip HC do not conform to a standard. In this case, the memory module, the positioning of the memory chips on the module circuit board and the bus architecture of the control bus have to be implemented in customized fashion. This is not desirable.